Intrinsic evolvable hardware for combinatorial synthesis based on SoC+FPGA and GPU platforms

Camargo Bareño, CarlosPedraza Bonilla, CesarNiño, Luis FernandoMartinez Torre, Jose2020-01-222020-01-222011-07http://hdl.handle.net/11634/21034This paper presents a novel a parallel genetic programming (PGP) boolean synthesis implementation on a low cost cluster of an embedded open platform called SIE. Some tasks of the PGP have been accelerated through a hardware coprocessor called FCU, that allows to evaluate individuals onchip as intrinsic evolution. Results have been compared with GPU and HPC implementations, resulting in speedup values up to approximately 2 and 180 respectivelyapplication/pdfAtribución-NoComercial-CompartirIgual 2.5 Colombiahttp://creativecommons.org/licenses/by-nc-sa/2.5/co/Intrinsic evolvable hardware for combinatorial synthesis based on SoC+FPGA and GPU platformsHardware copyleftEvolutionaryBoolean synthesishttps://doi.org/10.1145/2001858.2001964Generación de Nuevo Conocimiento: Artículos publicados en revistas especializadas - Electrónicos