Implementación del algoritmo Threefish-256 en hardware reconfigurable
| dc.creator | Nieto-Ramírez, Nathaly | |
| dc.creator | Nieto-Londoño, Rubén Darío | |
| dc.date | 2014-12-31 | |
| dc.date.accessioned | 2025-02-05T17:20:53Z | |
| dc.date.available | 2025-02-05T17:20:53Z | |
| dc.description | This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps. | en-US |
| dc.description | En este artículo se presenta la descripción y los resultados de la implementación en hardware del algoritmo criptográfico Threefish en su proceso de cifrado. La implementación se realizó usando la arquitectura de ronda iterativa sobre la Field Programmable Gate Array (FPGA) Virtex-5 presente en el sistema de desarrollo XUPV5-LX110T. Los resultados posteriores al place and route muestran que el diseño Threefish-256 de ronda iterativa tiene un throughput de 551Mbps. | es-ES |
| dc.format | application/pdf | |
| dc.identifier | https://revistas.ustabuca.edu.co/index.php/ITECKNE/article/view/725 | |
| dc.identifier | 10.15332/iteckne.v11i2.725 | |
| dc.identifier.uri | http://hdl.handle.net/11634/63114 | |
| dc.language | spa | |
| dc.publisher | Universidad Santo Tomás. Seccional Bucaramanga | en-US |
| dc.relation | https://revistas.ustabuca.edu.co/index.php/ITECKNE/article/view/725/571 | |
| dc.rights | Copyright (c) 2018 ITECKNE | en-US |
| dc.source | ITECKNE; Vol. 11 Núm. 2 (2014); 149-156 | es-ES |
| dc.source | ITECKNE; Vol. 11 No. 2 (2014); 149-156 | en-US |
| dc.source | 2339-3483 | |
| dc.source | 1692-1798 | |
| dc.subject | Cryptographic | en-US |
| dc.subject | FPGA | en-US |
| dc.subject | synchronous design | en-US |
| dc.subject | Threefish | en-US |
| dc.subject | VHDL | en-US |
| dc.subject | Criptografía | es-ES |
| dc.subject | diseño síncrono | es-ES |
| dc.subject | FPGA | es-ES |
| dc.subject | Threefish | es-ES |
| dc.subject | VHDL | es-ES |
| dc.title | Implementación del algoritmo Threefish-256 en hardware reconfigurable | es-ES |
| dc.title | Threefish-256 algorithm implementation on reconfigurable hardware | en-US |
| dc.type | info:eu-repo/semantics/article | |
| dc.type | info:eu-repo/semantics/publishedVersion |