Parallel algorithm for evolvable-based boolean synthesis on GPUs

Vista sencilla de ítem
dc.contributor.authorVitola, Jaimespa
dc.contributor.authorSanabria, Adrianaspa
dc.contributor.authorPedraza, Césarspa
dc.contributor.authorSepúlveda, Johannaspa
dc.coverage.campusCRAI-USTA Bogotáspa
dc.date.accessioned2020-01-22T17:31:12Zspa
dc.date.available2020-01-22T17:31:12Zspa
dc.date.issued2013-03-12spa
dc.description.abstractThe use of evolutionary algorithms in the boolean synthesis is an attractive alternative to generate interesting and efficient hardware structures, with a high computational load. This paper presents the implementation of a parallel genetic programming (PGP) for boolean synthesis on a GPU-CPU based platform. Our implementation uses the island model, that allows the parallel and independent evolution of the PGP through the multiple processing units of the GPU and the multiple cores of a new generation desktop processors. We tested multiple mapping alternatives of the PGP on the platform in order to optimize the PGP response time. As a result we show that our approach achieves a speedup up to 41 compared to CPU implementation.spa
dc.description.domainhttp://unidadinvestigacion.usta.edu.cospa
dc.format.mimetypeapplication/pdfspa
dc.identifier.doihttps://doi.org/10.1007/s10470-013-0059-1spa
dc.identifier.urihttp://hdl.handle.net/11634/21018
dc.relation.referencesAguirre, A., Coello, C., & Buckles, B. (1999). A genetic programming approach to logic function synthesis by means of multiplexers. Proceedings of the First NASA/DoD Workshop on Evolvable pp. 46 – 53.spa
dc.relation.referencesAmdahl, G.M. (1967). Validity of the single processor approach to achieving large scale computing capabilities. In: Proceedings of the April 18-20, 1967, spring joint computer conference, AFIPS ’67 Spring, (pp. 483–485). ACM, New York (1967). doi: 10.1145/1465482.1465560. URL http://doi.acm.org/10.1145/ 1465482.1465560.spa
dc.relation.referencesBremner, P., Samie, M., & Pipe, A. (2011). Multi-objective optimisation of cell-array circuit evolution. (CEC), 2011 IEEE (pp. 440–446).spa
dc.relation.referencesCharles, J., Jassi, P., Ananth, N.S., Sadat, A., & Fedorova, A. (2009). Evaluation of the Intel CoreTM i7 Turbo Boost feature. In: 2009 IEEE International Symposium on Workload Characterization (IISWC), (pp. 188–197). IEEE. doi:10.1109/ IISWC.2009.5306782.spa
dc.relation.referencesCoello, C., Zavala, R., & Garcı´a, B. (2000). Ant colony system for the design of combinational logic circuits. Evolvable Systems: From Biology to Hardware (pp. 21–30).spa
dc.relation.referencesEiben, A.E., & Smith, J. (2010). Introduction to evolutionary computing (Natural Computing Series). Heidelberg: Springer.spa
dc.relation.referencesGlette, K., & Torresen, J. (2005). A flexible on-chip evolution system Implemented on a Xilinx Virtex-II Pro Device. Evolvable Systems: From Biology to Hardware (pp. 66–75).spa
dc.relation.referencesGlette, K., Torresen, J., & Yasunaga, M. (2009). Online evolvable pattern recognition hardware. In: Evolutionary Image Analysis and Signal Processing, (pp. 41–54) Heidelberg: Springer.spa
dc.relation.referencesGoldberg, D., & Holland, J. (1988). Genetic algorithms and machine learning. Machine Learning, 3(2): 95–99.spa
dc.relation.referencesHarding, S., Miller, J.F., & Banzhaf, W. (2010). Developments in Cartesian genetic programming: self-pmodifying CGP. Genetic Programming and Evolvable Machines, 11(3-4):397–439 doi: 10.1007/s10710-010-9114-1.spa
dc.relation.referencesKajitani, I., Hoshino, T., Iwata, M., & Higuchi, T. (1996). Variable length chromosome GA for evolvable hardware. In: Proc. of the 3rd Int. Conf. on Evolutionary Computation, (pp. 443–447). Japan: Nagoya.spa
dc.relation.referencesKoza, J., Keane, M., Streeter, M., Mydlowec, W., & Yu, J. (2005). Genetic programming IV: routine human-competitive machine. Burlington: Morgan Kaufmann.spa
dc.relation.referencesLuong, T.V., Melab, N., & Talbi, E.G. (2010). GPU-based island model for evolutionary algorithms. In: Proceedings of the 12th annual conference on Genetic and evolutionary computation - GECCO ’10, (p. 1089). New York: ACM doi:10.1145/1830483.18 30685spa
dc.relation.referencesMoreno, J., Thoma, Y., & Sanchez, E. (2006). POETIC: a hardware prototyping platform with bio-inspired capabilities. In: Mixed Design of Integrated Circuits and System, 2006. MIXDES (pp. 363–368).spa
dc.relation.referencesNicholson, A. (2000). Evolution and Learning for Digital Circuit Design. In: Proceedings of Genetic and Evolutionary Computation Conf, (pp. 519–524).spa
dc.relation.referencesPedraza, C., Castillo, E., Castillo, J., Camarero, C., Bosque, J., Martinez, J., & Menendez, R. (2008). Cluster architecture based on low cost reconfigurable hardware. In: Field Programmable Logic and Applications, FPL 2008. International Conference on, (pp. 595–598) Heidelbergspa
dc.relation.referencesPedraza, C., Castillo, J., Martı´nez, J., & Huerta, P. (2011) Genetic Algorithm for Boolean minimization in an FPGA cluster. Journal of Supercomputing 58(2):244–252.spa
dc.relation.referencesRothlauf, F. (2006). Representations for genetic and evolutionay algorithms. Heidelberg: Springer.spa
dc.relation.referencesSekanina, L. (2009). Evolvable Hardware: From Applications to Implications for the theory of computation. In: Unconventional Computation,Lecture Notes in Computer Science, vol. 5715/2009, (pp. 24–36) Heidelberg: Springer.spa
dc.relation.referencesThoma, Y., Sanchez, E., & Hetherington, C. (2004). Prototyping with a bio-inspired reconfigurable chip. In: 15th IEEE International Workshop on Rapid System Prototyping.spa
dc.rightsAtribución-NoComercial-CompartirIgual 2.5 Colombia*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/2.5/co/*
dc.subject.keywordEvolutionary algorithmsspa
dc.subject.keywordBoolean synthesisspa
dc.subject.keywordGPUspa
dc.titleParallel algorithm for evolvable-based boolean synthesis on GPUsspa
dc.type.categoryGeneración de Nuevo Conocimiento: Artículos publicados en revistas especializadas - Electrónicosspa

Archivos

Bloque original

Mostrando 1 - 1 de 1
Miniatura
Nombre:
Parallel algorithm for evolvable-based boolean synthesis on GPUs.pdf
Tamaño:
660.4 KB
Formato:
Adobe Portable Document Format
Descripción:
Artículo SCOPUS
Descargar

Bloque de licencias

Mostrando 1 - 1 de 1
Thumbnail USTA
Nombre:
license.txt
Tamaño:
807 B
Formato:
Item-specific license agreed upon to submission
Descripción:
Descargar

Colecciones

Producción de Alto Impacto