Low cost high performance reconfigurable computing
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Abstract
High Performance Reconfigurable Computing (HPRC) has emerged as
an alternative way to accelerate applications using FPGAs. Although these HPRC
systems have a performance comparable to standard supercomputers and at a much
lower cost, HPRC systems are still not affordable for many institutions. We present a
low-cost HPRC system built on standard FPGA boards with an architecture that can
execute many scientific applications faster than in Graphical Processor Units and
traditional supercomputers. The system is made up of 32 low-cost FPGA boards and
a custom-made high-speed network interface using RocketIO interfaces. We have
designed a SystemC methodology and CAD framework that allow the designer to
simulate any MPI scientific application before generating the final implementation
files. The software runs on the PowerPC processor embedded in the FPGA on a
light ad-hoc implementation of MPI, and the hardware is automatically translated
from SystemC to Verilog, and connected to the PowerPC. This makes the SMILE
HPRC system fully compatible with any existing MPI application. The proof of
the concept of the SMILE HPRC has been exhaustively tested with two complex
and demanding applications: the Monte Carlo financial simulation and the Boolean
Synthesis using Genetic Algorithms. The results show a remarkable performance,
reasonable costs, small power consumption, no need of cooling systems, small
physical space requirements, system scalability and software portability.
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Atribución-NoComercial-CompartirIgual 2.5 Colombia