Intrinsic evolvable hardware for combinatorial synthesis based on SoC+FPGA and GPU platforms
Cargando...
Fecha
2011-07
Director
Enlace al recurso
ORCID
Google Scholar
Cvlac
gruplac
Descripción Dominio:
Título de la revista
ISSN de la revista
Título del volumen
Editor
Compartir
Documentos PDF
Cargando...
Resumen
Abstract
This paper presents a novel a parallel genetic programming
(PGP) boolean synthesis implementation on a low cost cluster of an embedded open platform called SIE. Some tasks
of the PGP have been accelerated through a hardware coprocessor called FCU, that allows to evaluate individuals
onchip as intrinsic evolution. Results have been compared
with GPU and HPC implementations, resulting in speedup
values up to approximately 2 and 180 respectively
Idioma
Palabras clave
Citación
Colecciones
Licencia Creative Commons
Atribución-NoComercial-CompartirIgual 2.5 Colombia